Buspirate and shift registers (a tale against publication bias)

As with most "publications," if you can call a blog post a publication, you're much more likely to read about what works than what doesn't. This is not that kind of post.

For background, I'm still working on my spectrum analyzer. I don't really like the current control board setup, and the windows-only BASIC software. I'm investigating other options for replacing those components. I'm thinking about using the 74595 shift registers to expand the number of control lines that I can control.

The basic idea of the 74595 is that it's a shift register with an extra set of output registers. The advantage is that you can load it "behind the scenes", then apply the output glitch free, and all at once. Essentially, you can treat it like a SPI peripheral. Load the pin values serially, then you can use the CS with the RCLK pin to load the output registers.

The schematic I used is included above. The basic model is that these devices can chain together. The serial data (delayed by 8 clock cycles) appears on QH*. This way, if we want 32 pins, we can chain 4 together. Load 32 bits of data onto the SPI bus and pulse the CS pin high. Hey presto, Bob's your uncle, you've got data.

The risk of this approach is that every operation on any of those pins takes 32 clock periods on the SPI bus. If the bus is clocked slowly, it can be a major problem. I had assumed that, because I can use a 4 MHz clock with the bus pirate, it would be alright. However, I hadn't anticipated the additional overhead that the bus pirate adds by using the serial port of a PC. Even using the binary scripting mode, you have to use 4 serial bytes for one 8-bit SPI transfer. The problem really stems from the inconsistent and bursty nature of the serial interface.

The bottom three traces on the above logic analyzer capture are the SPI commands to the registers. The top three are the SPI out from some of the register pins. Every change in the states of the top three requires a full load of the shift register. A SPI transfer out of the register requires 3 * bits + 2. The coefficient 3 is due to the expense of raising the clock pin, changing the data pin, and lowering the clock pin. The extra 2 is from raising and lowering the CS pin. Notice that it takes 1/3 of a second to execute a 40bit SPI transfer. To load a PLL requires several 21 bit loads, so it's about the same. This is unacceptable. That's the moral of the story. The bus pirate simply can't execute fast SPI commands through a shift register. Now you know. 😒